Allow configuration of Ethernet PHY clock source #916
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Refer to espressif/esp-idf#1127 The internal APLL can be used to generate the 50MHz clock for the internal EMAC and the external Ethernet PHY. The clock can either be input on GPIO0 (as before) or output on GPIO0, GPIO16 or GPIO17 (only GPIO17 extensively tested). New example available.
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travis seems to be missing some configuration files?!? |
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your sketch needs to be in it's own folder ;) currently Arduino will compile both sketches in that folder as one sketch. |
Refer to espressif/esp-idf#1127 The internal APLL can be used to generate the 50MHz clock for the internal EMAC and the external Ethernet PHY. The clock can either be input on GPIO0 (as before) or output on GPIO0, GPIO16 or GPIO17 (only GPIO17 extensively tested). New example available.
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ping. please merge. |
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pong done :) |
Curclamas
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Aug 21, 2018
* Allow configuration of Ethernet PHY clock source Refer to espressif/esp-idf#1127 The internal APLL can be used to generate the 50MHz clock for the internal EMAC and the external Ethernet PHY. The clock can either be input on GPIO0 (as before) or output on GPIO0, GPIO16 or GPIO17 (only GPIO17 extensively tested). New example available. * Allow configuration of Ethernet PHY clock source Refer to espressif/esp-idf#1127 The internal APLL can be used to generate the 50MHz clock for the internal EMAC and the external Ethernet PHY. The clock can either be input on GPIO0 (as before) or output on GPIO0, GPIO16 or GPIO17 (only GPIO17 extensively tested). New example available.
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Refer to espressif/esp-idf#1127
The internal APLL can be used to generate the 50MHz clock for the internal EMAC and the external Ethernet PHY.
The clock can either be input on GPIO0 (as before) or output on GPIO0, GPIO16 or GPIO17 (only GPIO17 extensively tested).
New example available.